This invention relates generally to integrated circuits, and more particularly to multiple input split adders capable of a split-add operation wherein two sets of operands are added simultaneously to increase computational throughput in a split add mode or capable of a hierarchical carry-select add operation to increase computational throughput in a hierarchical carry select add mode.
Addition forms the basis of many processing operations including counting, subtraction, multiplication, and filtering. A wide variety of adder circuits that add binary numbers provide an implementation with a trade-off between the speed of completing the addition operation and the amount of hardware, as measured by area required on an integrated circuit, to complete an addition operation. While three binary number representations are available, sign-magnitude, one""s complement, and two""s complement, computations are more efficient using the two""s complement number representation. Adders can be used to accomplish subtraction by generating the two""s complement of the subtrahend and adding the minuend. The two""s complement of the subtrahend can be generated internal to the adder by providing the subtrahend in one""s complement representation and adding one using the carry-in input to the adder.
A split adder is an adder that is capable of operating in a non-split mode on operands having a relatively large number of bits, and in split mode is capable of operating as more than one adder on operands having relatively fewer bits. In split mode operation, input vectors may be portioned into smaller vectors. The smaller vectors may be of the same number of bits or a different number of bits. In split mode operation, the operands to each adder comprising the split adder may be independent of other operands. Split adders are employed to take advantage of existing hardware where a tradeoff between precision and the number of adders can be made, and to gain additional computational throughput without requiring additional hardware. Split-adders in which the most significant bit portion of two operands are added in a first portion of an adder, and the least significant bit portions of two operands are added in a second portion of an adder are known. Known split-adders, however, can not accommodate more than two operands as inputs or hierarchical carry-select addition.
In accordance with the invention, an adder or an integrated circuit including an adder, includes a hierarchical carry-select split adder capable of operating in a split mode of operation when a mode select input takes on a first state, and is capable of operating in a hierarchical carry-select mode of operation when the mode select input takes on a second state.